1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, of improving a resistivity.
2. Discussion of the Related Art
In general, as the semiconductor devices are highly integrated, a width of wiring in the semiconductor devices is reduced, causing problems, such as drop in operation speed due to consequential increase of a resistance of the wiring. The formation of a thicker wiring as a wiring width is reduced used as a counter measure on the increased sheet resistivity of the wiring causes a problem that a fabrication process for the device becomes complicated with less yield because of a greater step coverage of the wiring. In order to solve these problems, a refractory metal silicide, such as tungsten silicide (WSi.sub.x), titanium silicide(TiSi.sub.2), or cobalt silicide(CoSi.sub.2) is formed on a polysilicon layer for preventing an increase of resistivity, (hereafter, a refractory metal silicide formed on a polysilicon layer is called "polycide"). However, though this can improve the resistivity and step coverage to a certain extent, an improved method for forming a polycide further is need.
A conventional method for fabricating a semiconductor device will be explained with reference to the attached drawings. FIGS. 1A-1C illustrate process steps of a first conventional method for fabricating a semiconductor device, and FIGS. 2A-2C illustrate process steps of a second conventional method for fabricating a semiconductor device. A polycide fabrication process used for reducing a resistivity and a step coverage in a semiconductor device can be applied to a process for forming a gate electrode or a bitline.
The process steps of the first conventional method for fabricating a semiconductor device in which the polycide fabrication process is applied to formation of a gate electrode will be explained.
Referring to FIG. 1A, the process starts with deposition of a first oxide film 2 on a semiconductor substrate 1 and deposition of a polysilicon layer 3 on the first oxide film 2. The polysilicon layer 3 is doped with P type impurities and soluble in water. The doping of the polysilicon layer 3 may be done by ion injection after deposition of the polysilicon layer 3 is completed, or by deposition of POCl.sub.3, or by a continuous injection of a doping gas, such as PH.sub.3, while depositing the polysilicon layer. For removing a natural oxide film(or glass) which may remain on the polysilicon layer 3 during the process of forming the polysilicon 3, the process resultant is dipped into HF solution for cleaning. A chemical vapor deposition of SH.sub.4 or SiH.sub.2 Cl.sub.2 with tungsten hexafluoride(WF.sub.6) gas is conducted to form a tungsten silicide layer 4, to form a polycide layer. As shown in FIG. 1C, the tungsten silicide layer 4, polysilicon layer 3 and the first oxide film 2 are subjected to photolithography to make an anisotropic etching of the layers 2, 3 and 4 with a mask for forming a gate electrode used, resulting to form a stack of a gate cap silicide layer 4a, a gate electrode 3a and a gate oxide film 2a. A lightly doped drain(LDD) region 5 is formed in the semiconductor substrate 1 on each side of the gate electrode 3a. A second oxide film is deposited on the entire surface and subjected to anisotropic etching to remove the second oxide film, forming sidewall insulating films 6 on both sides of the gate cap silicide layer 4a, gate electrode 3a and gate oxide film 2a. Portions of the semiconductor substrate 1 on outward sides of the sidewall insulating films 6, excluding a portion under the gate electrode 3a, are heavily doped, to form source/drain regions 7 therein.
The process steps of the second conventional method for fabricating a semiconductor device in which the polycide fabricating process is applied to formation of a bitline will be explained.
Referring to FIG. 2A, the process steps start with formation of an N type impurity doped layer 8 in a portion of a P type semiconductor substrate 1. A chemical vapor deposition is conducted to form an interlayer insulating layer 9 on the semiconductor substrate 1, which is selectively removed to form a contact hole 10 exposing the N type impurity doped layer 8. As shown in FIG. 2B, a polysilicon layer 11 is formed on the entire surface. The polysilicon layer 11 is doped with P type impurities and soluble in water. The doping of the polysilicon layer 11 may be done by ion injection after deposition of the polysilicon layer 3 is completed, or by deposition of POCl.sub.3, or by a continuous injection of a doping gas, such as PH.sub.3, while depositing the polysilicon layer. For removing a natural oxide film(or glass) which may remain on the polysilicon layer 11 during the process of forming the polysilicon 11, the process resultant is dipped into HF solution for cleaning. A chemical vapor deposition of SiH.sub.4 or SiH.sub.2 Cl.sub.2 with tungsten hexafluoride(WF.sub.6) gas is conducted to form a tungsten silicide layer 12 on the polysilicon layer 11, which is subjected to selective patterning to form a bitline of the polycide layer as shown in FIG. 2C.
However, the conventional methods for fabricating a semiconductor device have the following problems.
Because the gate electrode or the bitline in a semiconductor device formed by depositing tungsten silicide on a polysilicon layer according to the conventional methods shows the tungsten silicide to be non-amorphous with small granular sizes, the gate electrode or the bitline has a problem in reducing the resistivity of the polysilicon layer. Due to these reasons, the conventional methods for fabricating a semiconductor device can not serve for reducing the resistivity of the polysilicon in a highly packed device to a size no greater than 0.25 .mu.m.